Olivetti PCS 386SX

Intel 80386SX at 16 MHz with zero wait states and a 16-bit external data bus; optional Intel 80387SX at 16 MHz.

1 MB standard, expandable to 8 MB on the motherboard and 16 MB in the system; BIOS tests base and extended memory and stores configuration in 128-byte CMOS.

Integrated Paradise PVGA1A with 256 KB; OVC 1.06 video firmware is embedded in the known BIOS set.

Integrated IDE/ATA. Commercial configurations use two 1.44 MB floppy drives, or one floppy drive with a 20, 40 or 100 MB hard disk. The brochure does not identify exact drive models.

Confirmed physical population: Headland HT101SX + HT113 + GC102-PC three-chip set. BluMach models them as three separate devices and no longer reuses the HT18/HT21 core internally.

The exact HT101SX/HT113 data sheet has not been found. Board evidence and two independent BIOS families establish the 80386SX memory, shadow and EMS interface. BluMach assigns the firmware-visible memory controller to HT113, keeps HT101SX as the system-controller package and models GC102-PC as a transparent data buffer; this division is explicit and replaceable if primary documentation or hardware traces prove otherwise.

Both the PCS 386SX Phoenix 1.14 BIOS and another surviving HT101SX BIOS program 1ECh–1EFh: EMS mapping data, configuration index, EMS mapping address and configuration data. Neither BIOS accesses fast A20 port 92h, so the dedicated chipset does not install it.

TI TL16C451FN: one TL16C450-compatible UART plus a bidirectional Centronics printer interface. BluMach models that documented decomposition directly, replacing the unrelated PC87310 approximation.

Western Digital WD37C65CJM, represented by BluMach's AT-compatible uPD765 FDC core under the real component identity.

BIOS 1.14 with embedded OVC 1.06.

Extended Setup (F1–F10) stores in CMOS the clock, hard disk (12h), floppy drives A and B (10h), video (14h/1Ch), shadow RAM (none, BIOS, VGA or both), RAM test speed, the split between extended and EMS memory, RAM/IO/coprocessor clocks (16/8/16, 16/16/16 or 8/8/8 MHz), keyboard repeat rate, password and keyboard language. Checked in BluMach: the frequency setting is kept and 8/8/8 approximately slows memory. The 16 MHz I/O choice is stored, but the BIOS does not apply it. Keeping the shadow, EMS and drive B settings is still to be checked.

Customer Test exercises memory, clock, controllers and peripherals. U_MGR from the preserved copy hangs and remains under investigation to distinguish disk damage from an emulation incompatibility.

Two 64 KB LOW/HIGH images are byte-interleaved into 128 KB at E0000h–FFFFFh. The global eight-bit checksum is zero. The first 24 KB contain OVC 1.06.

At F000:37C6 (physical F37C6h), Phoenix sends AEh to the 8042, waits for OBF at 64h and requires 3Bh from 60h. The generic 8042 only enabled the keyboard and left BIOS waiting; BluMach queues one machine-specific 3Bh response.

Selector is at 68h, data/status at 6Ah, with an additional 6Ch register. Phoenix 1.14 verifies 55h/AAh writes and expects 6Ah reads to apply XOR 20h; with selector 00h a write must not latch. Warm reset restores 04h/04h/FFh.

The provisional HT113 device exclusively owns conventional memory, 384 KB relocation, shadow RAM and EMS. With CR0 bit 2 clear, the 384 KB hidden by the upper-memory area is relocated above 1 MB. BIOS 1.14 does not contain the PCS 286 RAM-REMAPPING 60000h/80000h test; that copied alias and the generic AT remap were removed because they overlap the controller's maps.

128-byte Phoenix CMOS. BIOS 1.14 encodes 80x25 internal video as video bits 00h in CMOS 14h plus 20h in CMOS 1Ch; 80x25 external uses 20h in 14h plus 00h in 1Ch. The 80387SX updates bit 1 of 14h, and every change requires the 10h–2Dh checksum to be recalculated.

OVC 1.06 is embedded in the system BIOS and controls the integrated 256 KB PVGA1A; therefore the device does not mount an external Paradise ROM at C0000h.

Usable partial emulation: BIOS 1.14 POST and MS-DOS boot at 1, 2, 4 and 8 MB; Built-In Setup, internal PVGA1A/OVC 1.06 video, keyboard, CMOS/RTC, floppy and optional 80387SX diagnostics. The IOC02 self-test passes. An instrumented 8042 reset-entry probe confirms that CRI, MAR, CR0–CR4 and MR state survive a soft reset, while a hard reset recreates cold defaults.

Status: partial and bootable, not cycle-exact. IDE installation, persistence and second boot remain pending. No exact HT101SX/HT113 data sheet or original M5L8042 keyboard-controller ROM is public, so the register ownership and keyboard protocol are BIOS-derived functional models. GC102-PC parity/NMI wiring, physical HT113 warm-reset behaviour and EMS page mapping still need original hardware or diagnostics. General software compatibility has not yet been surveyed, and the preserved Customer Utility U_MGR module hangs; its disk history and DOS/Barrotes_1310 detection prevent treating that result as a confirmed emulator fault. The password keyboard-lock mode is not emulated, and the keyboard repeat rate follows the host computer.